The present invention relates to a parallel counter constructed as an integrated circuit using MOS transistors, with n inputs and (n+1) outputs and an application of this counter in the construction of a binary adder.
The possibility of an adder permitting the addition of a large number of bits in parallel is of particular interest for the construction of a multiplier in which it is necessary to add in parallel several binary elements representing the partial products of the same order. In MOS logic, that is to say in the case of integrated logic circuits using MOS transistors, it is customary to use three-input two-output adders. The problems of carry propagation and the algorithms used to overcome the delays introduced by the time required for carry propagation are well known. However, the logic information will in any case have to pass through a certain number of gates, usually EXCLUSIVE OR gates, each containing several of these MOS transistors, and its speed of operation will be greatly affected.